(1) Field of the Invention
The present invention relates to processes used to fabricate semiconductor devices, and more specifically to a process used to fabricate a non-volatile memory device.
(2) Description of the Prior Art
Non-volatile memory devices, such as Electrical Erasable Programmable Read Only Memory, (EEPROM), or Erasable Programmable read Only Memory, (EPROM), devices, offer the desirable features of programming, reading, and erasing, via use of only specific biasing procedures. One form of these devices, is comprised of a "split gate" electrode configuration, in which the control gate overlies all, or a portion of an underlying floating gate, and overlies a portion of the channel region. The use of the split gate electrode configuration can however result in the formation of trenches, in an active device region of the non-volatile memory device, during the formation of the polysilicon control gate structure. For example if a self-aligned, control gate to floating gate configuration is desired, the final pattern for the underlying polysilicon floating gate structure, is defined during the polysilicon control gate patterning. This procedure can result in unwanted trenches in active regions of the semiconductor substrate, in regions in which the polysilicon control gate structure, does not overlay the polysilicon floating gate structure. The additional etching time, needed to define the combination of gates, in regions in which the control gate overlays the floating gate, can result in undesirable trench formation, in regions in which the gates do not overlay.
This invention will describe a reactive ion etching, (RIE), patterning procedure, allowing successful self-alignment, simultaneously forming the entire polysilicon control gate, and a final definition of an underlying polysilicon floating gate structure, without degradation to active device regions, in areas not covered by either gate structure. This is achieved using a unique, initial, polysilicon floating gate layout. Prior art, such as Chung, in U.S. Pat. No. 5,643,814, describe a method of forming an EEPROM device, however without the simultaneous definition of both gate structures.